Active devices in integrated circuits require one or more power supplies. For many logic families, Direct Current (DC) power sources are required. Instead of supplying all possible values of voltage and current used in the circuit, a standard approach is to use networks of resistors to distribute the power among the various bias nodes of the circuit with appropriate values. This is the case, for example, in typical superconducting circuits comprising Josephson junctions designed according to rapid-single-flux-quantum (RSFQ) logic, as shown in FIG. 1 of the prior art. Conventional RSFQ logic is reviewed in “RSFQ Logic/Memory Family”, K. K. Likharev and V. K. Semenov, IEEE Transactions on Applied Superconductivity, vol. 1, pp. 3-28, March 1991, incorporated herein by reference. Each ‘X’ in FIG. 1 represents a damped Josephson junction with a DC I-V curve as shown in FIG. 2. The parallel array of Josephson junctions represents a simple RSFQ circuit, the Josephson transmission line (JTL). Each Josephson junction is typically biased with a dc current below its critical current IC, so that it exhibits V=0 and dissipates no power in its static state. For currents just above IC, the junction generates a sequence of voltage pulses, with each voltage pulse having an identical time integral∫Vdt=Φ0=h/2e=2.07 mv-ps,
which is known as the single flux quantum or SFQ. For typical parameters, the pulse height is about 1 mV and the pulse width about 2 ps. Operation of an RSFQ circuit corresponds to distribution and switching of individual SFQ pulses. A typical pulse data rate may be f=40 GHz, corresponding to a time-averaged voltage of Φ0f=80 μV. In contrast, the DC bias voltage applied to the bias resistors may be 5 mV, a factor of 60 larger. So, the overwhelming majority of the power dissipation in the circuit occurs in the static power distribution resistors.
Superconductor single flux quantum technology is based on manipulation of magnetic flux quanta Φ0=h/2e with energy of ˜2×10−19 Joule or 5×103 kBT ln(2) at T=4K or 70 kBT ln(2) at T=300K. Low power, high speed, and high sensitivity of superconductor Rapid Single Flux Quantum (RSFQ) technology (see, K. Likharev and V. Semenov, “RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz clock-frequency digital systems”, IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991) have already attracted much attention for digital and mixed signal applications.
The problem of static power dissipation in RSFQ logic was discussed since its invention in 1987. It was widely perceived at the time, that solving this problem is not very urgent while demonstrating small-scale devices, and with time, when its topicality should arise, surely will be solved. Since then, a number of attempts to negate the power dissipation in bias resistors of RSFQ circuits has been undertaken. See, A. Rylyakov, “New design of single-bit all-digital RSFQ autocorrelator”, IEEE Trans. Appl. Supercond., vol. 7, pp. 2709-2712, June 1997; A. Rylyakov and K. Likharev, “Pulse jitter and timing errors in RSFQ circuits”, IEEE Trans. Appl. Supercond., vol. 9, pp. 3539-3444, June 1999; S. Polonsky, “Delay insensitive RSFQ circuits with zero static power dissipation,” IEEE Trans. Appl. Supercond., vol. 9, pp. 3535-3538, June 1999.
The first and the most practical idea was reducing value of a bias resistor by serially connecting it with large superconducting inductance. A moderate-size circuit has been designed using this approach and successfully tested at low speed. Unfortunately, RSFQ circuits, biased with such a scheme, can only operate at frequencies much smaller than Vbias/Φ0. So, reducing bias resistors simultaneously reduces the maximum clock frequency. Besides, this approach reduces somewhat but does not eliminate static power dissipation.
A more radical approach was developing alternatives to RSFQ logic, e.g. S. Polonsky, “Delay insensitive RSFQ circuits with zero static power dissipation,” IEEE Trans. Appl. Supercond., vol. 9, pp. 3535-3538, June 1999; and A. H. Silver, Q. P. Herr, “A new concept for ultra-low power and ultra-high clock rate circuits,” IEEE Trans. Appl. Supercond., vol. 11, pp. 333-336, June 2001. None of these ideas was practical and beneficial enough to become accepted. The recently suggested RQL logic (Q. P. Herr, “Single Flux Quantum Circuits,” U.S. Pat. No. 7,724,020, May 25, 2010) looks very attractive in terms of power dissipation, but requires multi-phase ac power, which makes the implementation of high-speed VLSI circuits very difficult.
Meanwhile, with the maturity of RSFQ technology, the elimination of static and reducing total power dissipation has become a very important problem in the field of superconductor microelectronics. In the emerging fields of digital readout for cryogenic detector arrays and qubit control circuitry for quantum computing, static power dissipation of standard RSFQ circuits is considered too large for the required readout and control circuits.
Another aspect of the prior art is that a damped Josephson junction generally comprises a superconducting tunnel junction in parallel with a shunt resistor, where the resistor is deliberately added to increase the device damping (see FIG. 3). An underdamped junction will tend to oscillate rather than generating SFQs, and have a hysteretic I-V curve unlike that in FIG. 2; such underdamped junctions are typically avoided in RSFQ circuits. The value of the shunt resistor is selected to obtain critical damping of the junction. The value of the bias resistor for supplying current to a Josephson junction is typically a factor of ten larger than the shunt resistor, in order to provide sufficient control and isolation of the currents in the various bias lines.
This resistive bias tree functions well to provide circuits that operate at clock frequencies up to 40 GHz and above, with maximum stability. However, the same resistor network substantially reduces one of the key advantages of RSFQ circuits, the extremely low power dissipation. The overwhelming majority of the power dissipation is associated not with the logic circuits, but rather with Joule heating in the power distribution resistors. For the typical parameters given above, only about 1/60th or less than 2% of the power is intrinsic to the dynamic active devices; the rest is static heating in the bias resistors.
Even with heating in the bias resistors, RSFQ is a low-power technology. Nevertheless, it is important to keep power dissipation low for several reasons. First, as the device scale decreases and the packing density increases, the power density will increase substantially, causing local heating of the devices. Second, the total power is also increasing with circuit complexity. This would allow one to realize a significant (˜orders of magnitude) advantage over semiconductor CMOS circuits in switching power (FIG. 4). Third, this power must be removed at cryogenic temperatures, using inefficient refrigerators, so that the total electrical power at room temperature is many times larger than the cryogenic heat load. Further, as thermal isolation techniques improve, the intrinsic thermal load of the operating circuit will become relatively more important as a factor in determining the size of the refrigerator necessary to operate the system.
It is useful to distinguish the DC and AC properties of a superconducting logic circuit biasing network. The network must maintain the proper current biases on average (at DC), but also must maintain these proper biases on very short times, against transients and fluctuations that might tend to change the biases in a given branch. This is particularly important for RSFQ circuits, since these generate picosecond pulses, changing the gate impedance on this time scale from zero to an impedance of typically several ohms, and back again. A change in load on this timescale must not divert current into other branches of the network.
Clearly, a resistive network, where the resistances are much larger than the largest transient impedance of the loads, will work at both DC and at AC. A purely inductive network will work at AC but not at DC. This DC problem can be fixed by adding a series R to each L, such that the DC impedances are also properly balanced. This value of R in each leg must be much greater than the DC average impedance of each gate. This can result in a significant reduction in power dissipation, relative to a purely resistive network. However, the static power dissipation in the bias network will still be much larger than the dynamic power dissipation in the gates, which is undesirable in certain applications.
There is a further problem with a network comprised of superconducting inductors L. Because of the quantum nature of superconductors, any superconducting loop must quantize the magnetic flux in the loop in integral multiples of the single flux quantum Φ0=h/2e=2 pH-mA, corresponding to a net circulating current LI=Φ0 that never dies out. A series resistance will cause this current to die out very quickly, at a cost of power dissipation.
Eaton et al, U.S. Pat. No. 7,002,366, expressly incorporated herein by reference, propose a biasing scheme for superconducting gates that uses resistively shunted Josephson junctions (RSJs) as bias elements, based on their DC I-V characteristics. For a current equal to or slightly greater than the critical current IC of the RSJ, the current is almost constant, corresponding (for a range of voltages) to a constant current supply (see prior art FIG. 2). This might seem to be ideal for a bias current network for an array of superconducting gates. However, Eaton's design, as disclosed, will not function properly in practice, because the DC I-V curve of the RSJ does not apply for short times. Eaton notes that the RSJ is an oscillator at AC for I>IC, and suggests applying an unspecified “damping impedance” in series with the RSJ, where this damping impedance may include one or more of a resistor, or an inductor, or a capacitor. This scheme also suggests using JJs in the resistive state (i.e. I>IC), thus creating static power dissipation even while the circuit is in idle mode.
Eaton also does not address a bias network with multiple gates, in which any two parallel legs of the network form a Superconducting Quantum Interference Device (SQUID), which is well known in the prior art as a sensitive quantum-limited detector of magnetic flux. The I-V curve of a SQUID shows that the critical current IC is strongly modulated by flux periodically in Φ0. Such a small change in flux may be introduced not only by an external magnetic field, but also by stray inductance and transient currents. So the bias current in a given leg of an array is not determined simply by the I-V curve of a single junction. This SQUID effect can be reduced by adding a series resistance in the loop, breaking the superconducting order, but this would also increase the static dissipated power.